The present invention relates to a semiconductor device manufacturing technique and more particularly to a technique applicable effectively to stabilizing the quality of a semiconductor device having a plurality of semiconductor chips.
As a semiconductor device having a plurality of semiconductor chips, for example in Japanese Unexamined Patent Publication No. 2005-303222 (Patent Document 1) there is described a structure in which a microcomputer chip and a SDRAM are arranged side by side. Further, in Japanese Unexamined Patent Publication No. 2005-327967 (Patent Document 2) is described a structure having a first chip and a second chip bonded horizontally to die pads respectively and further having wires, the wires being bonded at one ends thereof to an upper surface of the first chip and at opposite ends thereof to upper surfaces of leads after jumping over the second chip.